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'dwd 6khhw 2ughu 1r 0' 5hy 'hfhpehu 53/'53/'dqg53/' /rz9rowdjh9.ioh[ ? 99elv 0rghp'dwd3xpsviru/rz3rzhu$ssolfdwlrqv introduction the conexant ? RP56LD, rp336ld, and rp144ld modem data pump (mdp) families support data/fax modem, voice coding/decoding, optional full-duplex speakerphone, and optional audiospan (table 1). low voltage and low power consumption support portable applications. downloadable architecture allows upgrading of mdp code from the host/dte. in v.90/k56flex mode (rp56), the mdp can receive data at speeds up to 56 kbps from a digitally connected v.90- or k56flex-compatible central site modem. these mdps take advantage of the pstn which is primarily digital except for the client modem to central office local loop and are ideal for applications such as remote access to an internet service provider (isp), on-line service, or corporate site. the mdp can send upstream data at speeds up to v.34 rates. in v.34 data mode (rp56 and rp336), the mdp can connect at the highest data rate the channel can support from 33.6 kbps to 2400 bps with auto-fallback to v.32bis. in v.32 bis mode, the mdp can connect at the highest data rate the channel can support from 14.4 kbps to 4800 bps with optional auto-fallback to lower rate modulations. internal hdlc support eliminates the need for an external serial input/output (sio) device in the dte for products incorporating error correction and t.30 protocols. voice mode includes an adaptive differential pulse code modulation (adpcm) voice coder and decoder (codec). the codec compresses and decompresses voice signals for efficient digital storage of voice messages. the codec operates at 28.8k, 21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit quantization, respectively) with a 7.2 khz or 8.0 khz sample rate. a voice pass-through mode allows the host to transmit and receive uncompressed voice samples in 16-bit linear form at 7.2 khz, 8.0 khz, or 11.025 khz sample rate, or in 8-bit a-law/-law pcm form at 8.0 khz sample rate. sp models support position-independent full-duplex speakerphone (fdsp) operation using a dual internal integrated analog circuit to interface with the telephone line and the audio input/out (i.e., a headset, handset, or a microphone with external speaker). sp models in 144-pin tqfp also support a 4-line voice serial interface used to transfer 16-bit linear or 8-bit a- law/-law pcm fdsp voice samples with acoustic echo cancellation to and from the host. sp models also support audiospan (analog simultaneous audio/voice and data) operation at a data rate of 4.8 kbps. the mdp operates over the public switched telephone network (pstn) through the appropriate line termination. features downloadable mdp code from the host/dte 2-wire full-duplex - v.90 and k56flex (rp56 models) - v.34 (33.6 kbps) (rp56 and rp336 models) - v.32 bis, v.32, v.22 bis, v.22, v.23, and v.21 - bell 212 and 103 2-wire half-duplex - v.34 fax, v.17, v.33, v.29, v.27 ter, and v.21 ch 2 - bell 208 - short train option in v.17 and v.27 ter serial synchronous and asynchronous data parallel synchronous and asynchronous data parallel synchronous sdlc/hdlc support in-band secondary channel (v.34 and v.32 bis) automatic mode selection (ams) automatic rate adaption (ara) digital near-end and far-end echo cancellation bulk delay for satellite transmission adpcm voice mode (7.2 khz or 8.0 khz) voice pass-through mode (7.2 khz, 8.0 khz, or 11.025 khz) full-duplex speakerphone (sp models) - acoustic and line echo cancellation - programmable microphone agc - microphone volume selection and muting - speaker volume control and muting; room monitor voice serial data interface (144-pin tqfp, sp models) - 16-bit linear or 8-bit a-law/-law pcm voice samples - fdsp support with acoustic echo cancellation audiospan (sp models) - itu-t v.61 modulation (4.8 kbps data plus audio) - handset, headset, or half-duplex speakerphone ttl and cmos compatible dte interface - itu-t v.24 (eia/tia-232-e) (data/control) - microprocessor bus (data/configuration/control) dynamic range: -9 dbm to -43 dbm adjustable speaker output to monitor received signal dma support interrupt lines transmit and receive (16+128)-byte fifo data buffers nrzi encoding/decoding 511 pattern generation/detection v.8 and v.8 bis signaling v.13 signaling diagnostic capability - v.54 inter-dce signaling - v.54 local analog and remote digital loopback +3.3v operation with +5v tolerant inputs - +5v or +3.3v analog signal interface low power consumption: - normal mode = 260 mw; sleep mode = 40 mw low profile, small footprint package - 100-pin pqfp or 144-pin tqfp - meets pc card type ii envelope requirements
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' 7deoh 0rghp 0rghov dqg )xqfwlrqv 0rghp3duw 1xpehu 3dfndjh dqg 3dfndjh 2swlrqv 6xssruwhg )xqfwlrqv 0rgho 1xpehu 3duw 1r 3dfndjh &orfn&u\vwdo ,qsxw $qdorj ,qwhuidfh 9rowdjh 9.ioh[ 'dwd 9 'dwd 9 elv 'dwd 9 )d[ 5hprwh 9rlfh )'63 $xglr6sdq 9rlfh 6huldo ,qwhuidfh 53/'63 5 3lq 34)3 &orfn 9 < < < < 53/' 5 3lq 34)3 &orfn 9 < < < 53/'63 5 3lq 34)3 &orfn 9 < < < 53/' 5 3lq 34)3 &orfn 9 < < 53/'63 5 3lq 34)3 &orfn 9 < < 53/' 5 3lq 34)3 &orfn 9 < 53/'63 5 3lq 74)3 &orfn&u\vwdo 99 < < < < < 53/' 5 3lq 74)3 &orfn&u\vwdo 99 < < < 53/'63 5 3lq 74)3 &orfn&u\vwdo 99 < < < < 53/' 5 3lq 74)3 &orfn&u\vwdo 99 < < 1rwhv 0rghosduw qxpehu rswlrqv / /rz srzhu ' 'rzqordgdeoh 63 6shdnhuskrqh 6xssruwhg ixqfwlrqv < 6xssruwhg 1rw vxssruwhg )'63 )xoogxsoh[ vshdnhuskrqh 5hprwh 9rlfh 5hprwh yrlfh uhfrug dqg sod\edfn $xglr6sdq $qdorj vlpxowdqhrxv yrlfh dqg gdwd information provided by conexant systems, inc. is believed to be accurate and reliable. however, no responsibility is assumed b y conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. no license is granted by implicatio n or otherwise under any patent rights of conexant other than for circuitry embodied in conexant products. conexant reserves the right to change circuitry at any time wi thout notice. this document is subject to change without notice. k56flex is a trademark of conexant systems, inc. and lucent technologies. conexant and what's next in communications technologies are trademarks of conexant systems, inc. ?1998, conexant systems, inc. printed in u.s.a. all rights reserved
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' technical description the mdp functional interface is illustrated in figure 1. configurations and rates the selectable mdp configurations, signaling rates, and data rates are listed in table 2. md212f1 fid rs0-rs4 crystal circuit xtli** xtlo** telephone line/ telephone/ audio interface interface telephone line ~rlya ~rlyb ringd rin txa1 txa2 micm spk spkmd micv/nc* telin/nc* telout/nc* rxa txa vcc (+3.3v) agnd dgnd power supply host processor decoder ~cs ~read ~write data bus (8) d0-d7 address bus (5) a0-a4 ~reset irq mic/ speaker spkr mic telephone line telout telin v.24 serial dte interface ~rdclk tdclk xtclk txd rxd ~rts ~cts ~dtr ~dsr ~rlsd ~ri modem data pump (mdp) [r6785: 144-pin tqfp r6764: 100-pin pqfp] vgg (+5v or 3.3v) clock circuit clkin** * pins are internal no connect (nc) on non-sp models. ** separate pins for clock and crystal input on r6785 144-pin tqfp with use determined by input control signal; r6764 100-pin pqfp supports clock input only. *** voice serial interface supported for r6785 144-pin sp model. vaa (+3.3v) host processor sr8out*** sr8in*** sr4clk*** sa4clk*** )ljxuh 0'3 )xqfwlrqdo ,qwhuidfh
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' 7deoh &rqiljxudwlrqv 6ljqdolqj 5dwhv dqg 'dwd 5dwhv &rqiljxudwlrq 0rgxodwlrq &duulhu )uhtxhqf\ +] ? 'dwd 5dwh esv ? 6\pero 5dwh 6\perov6hf %lwv6\pero 'dwd %lwv6\pero 7&0 &rqvwhoodwlrq 3rlqwv v.90/k56flex pcm* pcm C 56000r/v.34ratest 4 8000 dynamic C C v.34 33600 tcm** tcm note 2 33600 note 2 note 2 note 2 note 2 v.34 31200 tcm** tcm note 2 31200 note 2 note 2 note 2 note 2 v.34 28800 tcm** tcm note 2 28800 note 2 note 2 note 2 note 2 v.34 26400 tcm** tcm note 2 26400 note 2 note 2 note 2 note 2 v.34 24000 tcm** tcm note 2 24000 note 2 note 2 note 2 note 2 v.34 21600 tcm** tcm note 2 21600 note 2 note 2 note 2 note 2 v.34 19200 tcm** tcm note 2 19200 note 2 note 2 note 2 note 2 v.34 16800 tcm** tcm note 2 16800 note 2 note 2 note 2 note 2 v.34 14400 tcm** tcm note 2 14400 note 2 note 2 note 2 note 2 v.34 12000 tcm** tcm note 2 12000 note 2 note 2 note 2 note 2 v.34 9600 tcm** tcm note 2 9600 note 2 note 2 note 2 note 2 v.34 7200 tcm** tcm note 2 7200 note 2 note 2 note 2 note 2 v.34 4800 tcm** tcm note 2 4800 note 2 note 2 note 2 note 2 v.34 2400 tcm** tcm note 2 2400 note 2 note 2 note 2 note 2 v.32 bis 14400 tcm tcm 1800 14400 2400 6 1 128 v.32 bis 12000 tcm tcm 1800 12000 2400 5 1 64 v.32 bis 9600 tcm tcm 1800 9600 2400 4 1 32 v.32 bis 7200 tcm tcm 1800 7200 2400 3 1 16 v.32 bis 4800 qam 1800 4800 2400 2 0 4 v.32 9600 tcm tcm 1800 9600 2400 4 1 32 v.32 9600 qam 1800 9600 2400 4 0 16 v.32 4800 qam 1800 4800 2400 2 0 4 v.22 bis 2400 qam 1200/2400 2400 600 4 0 16 v.22 bis 1200 dpsk 1200/2400 1200 600 2 0 4 v.22 1200 dpsk 1200/2400 1200 600 2 0 4 v.22 600 dpsk 1200/2400 600 600 1 0 4 v.23 1200/75 fsk 1700/420 1200/75 1200 1 0 C v.21 fsk 1080/1750 0C300 300 1 0 C bell 208 4800 dpsk 1800 4800 1600 3 0 8 bell 212a dpsk 1200/2400 1200 600 2 0 4 bell 103 fsk 1170/2125 0C300 300 1 0 C v.23 1200/75 fsk 1700/420 1200/75 1200 1 0 C v.21 fsk 1080/1750 0C300 300 1 0 C v.17 14400 tcm/v.33 3 tcm 1800 14400 2400 6 1 128 v.17 12000 tcm/v.33 3 tcm 1800 12000 2400 5 1 64 v.17 9600 tcm 3 tcm 1800 9600 2400 4 1 32 v.17 7200 tcm 3 tcm 1800 7200 2400 3 1 16 v.29 9600 3 qam 1700 9600 2400 4 0 16 v.29 7200 3 qam 1700 7200 2400 3 0 8 v.29 4800 3 qam 1700 4800 2400 2 0 4 v.27 4800 3 dpsk 1800 4800 1600 3 0 8 v.27 2400 3 dpsk 1800 2400 1200 2 0 4 v.21 channel 2 3 fsk 1750 300 300 1 0 C tone transmit C C C C C C C notes: 1. modulation legend: tcm: trellis-coded modulation qam: quadrature amplitude modulation fsk: frequency shift keying dpsk: differential phase shift keying 2. adaptive; established during handshake: &duulhu )uhtxhqf\ +] 6\pero 5dwh %dxg 9 /rz &duulhu 9 +ljk &duulhu 3. models with fax support only. 4. maximum data rate. * rp56 models only. ** rp56 and rp336 models only.
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' automatic mode selection when automatic mode selection (ams) is enabled, the mdp configures itself to the highest compatible data rate supported by the remote modem (auto bit). automode operation is supported in v.90, k56flex, v.34, v.32 bis, v.32 v.22 bis, v.22, v.21, v.23, bell 212a, and bell 103 modes. automatic rate adaption (ara) in v.90, k56flex, v.34, and v.32 bis modes, automatic rate adaption (ara) can be enabled to select the highest data rate possible based on the measured eye quality monitor (eqm) (earc bit). this selection occurs during handshake/retrain and rate renegotiation. tone generation the mdp can generate single or dual voice-band tones from 0 hz to 3600 hz with a resolution of 0.15 hz and an accuracy of 0.01%. tones over 3000 hz are attenuated. dtmf tone generation allows the mdp to operate as a programmable dtmf dialer. data encoding the data encoding conforms to itu-t recommendations v.90, v.34, v.32 bis, v.32, v.17, v.33, v.29, v.27 ter, v.22 bis, v.22, v.23, or v.21, and is compatible with bell 208, 212a, or 103, depending on the model and selected configuration. rts - cts response time the response times of cts relative to a corresponding transition of rts are listed in table 3. transmit level the transmitter output level is selectable from -4 dbm to -19 dbm (vaa = +3.3v) or 0 dbm to -15 dbm (vaa = +5v) in 1 db steps and is accurate to 0.5 db when used with an external hybrid. the output level can also be fine tuned by changing a gain constant in mdp dsp ram. the maximum v.34/v.32 bis/v.32 transmit level for acceptable receive performance should not exceed -9 dbm. note: in v.34 mode, the transmit level may be automatically changed during the handshake. this automatic adjustment of the transmit level may be disabled via a parameter in dsp ram. transmitter timing transmitter timing is selectable between internal (0.01%), external, or slave. scrambler/descrambler a self-synchronizing scrambler/descrambler is used in accordance with the selected configuration. answer tone when the nv25 bit is a zero, the mdp generates a 2100 hz answer tone at the beginning of the answer handshake for 5.0 seconds (v.8) or 3.6 seconds (v.32 bis, v.32, v.22 bis, v.22, v.23, and v.21). the answer tone has 180 phase reversals every 0.45 second to disable network echo cancellers (v.8, v.32 bis, v.32). 7deoh 576&76 5hvsrqvh 7lphv rts-cts response 1 configuration constant carrier controlled carrier turn-off sequence 3 v.90, k56flex, v.34, v.32 bis, v.32 2 ms n/a n/a v.33/v.17 long n/a 1393 ms 2 15 ms 4 v.33/v.17 short n/a 142 ms 2 15 ms 4 v.29 n/a 253 ms 212 ms v.27 4800 long n/a 708 ms 2 7 ms 4 v.27 4800 short n/a 50 ms 2 7 ms 4 v.27 2400 long n/a 943 ms 2 10 ms 4 v.27 2400 short n/a 67 ms 2 10 ms 4 v.22 bis, v.22, bell 212a 2 ms 270 ms n/a v.21 500 ms 500 ms n/a v.23, bell 103 210 ms 210 ms n/a notes: 1. times listed are cts turn-on. the cts off-to-on response time is host programmable in dsp ram. (full- duplex modes only.) 2. add echo protector tone duration plus 20 ms when echo protector tone is used during turn-on. 3. turn-off sequence consists of transmission of remaining data and scrambled ones for controlled carrier operation. cts turn-off is less than 2 ms for all configurations. 4. plus 20 ms of no transmitted energy. 5. n/a = not applicable. receive level the mdp satisfies performance requirements for received line signal levels from C9 dbm to C43 dbm measured at the receiver analog (rxa) (tip and ring) input (-15 dbm at rin). note: a 6 db pad is required between tip and ring and the rin input. receiver timing the timing recovery circuit can track a frequency error in the associated transmit timing source of 0.035% (v.22 bis) or 0.01% (other configurations). carrier recovery the carrier recovery circuit can track a 7 hz frequency offset in the received carrier. clamping received data (rxd) is clamped to a constant mark whenever the received line signal detector (~rlsd) is off. ~rlsd can be clamped off (rlsde bit).
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' echo canceller a data echo canceller with near-end and far-end echo cancellation is included for 2-wire full-duplex v.34/v.32 bis/v.32 operation. the combined echo span of near and far cancellers can be up to 40 ms. the proportion allotted to each end is automatically determined by the mdp. the delay between near-end and far-end echoes can be up to 1.2 seconds. v.90 and k56flex echo cancellation is also provided. adpcm voice mode the adaptive differential pulse code modulation (adpcm) voice coder and decoder (codec) compresses and decompresses voice signals for efficient digital storage of voice messages. the codec operates at 28.8k, 21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit quantization, respectively) with a 7.2 khz or 8.0 khz sample rate. transmit voice. 16-bit compressed transmit voice can be sent to the mdp adpcm codec for decompression then to the digital-to-analog converter (dac) by the host. receive voice. 16-bit received voice samples from the mdp analog-to-digital converter (adc) can be sent to the adpcm codec for compression, and then be read by the host. voice pass-through mode voice pass-through mode allows the host to transmit and receive uncompressed voice samples in 16-bit linear form at 7.2 khz, 8.0 khz, or 11.025 khz sample rate, or in 8-bit a-law/-law pcm form at 8.0 khz sample rate. transmit voice. transmit voice samples can be sent to the mdp dac from the host. receive voice. received voice samples from the mdp adc can be read by the host. speakerphone voice/audio paths (sp models) the mdp incorporates a dual integrated analog interface. the voice/audio transmit and receive signals can be routed through several paths. the voice/audio paths are available in the speakerphone mode configuration and are selected through dsp ram. the voice/audio input can be taken from one of four different sources: telephone line input (rin), handset (telin), microphone (micm or micv). the speaker output (spk) can originate from one of five different sources: rin, telin, micm or micv or from the mdps internal voice playback mode. the voice/audio output may be routed to the telephone line output (txa1 and txa2) or handset (telout). the voice paths can be switched to allow an audio input to be routed to the telephone line output through a variable gain for applications such as music-on-hold. the room monitor mode allows the mdp to receive audio from its surroundings and concurrently transmit the audio to a remote site. voice serial interface (sp models in 144-pin tqfp) a 4-pin serial interface supports the transfer of 16-bit linear or 8-bit a-law/-law pcm voice samples in full- duplex speakerphone form with acoustic echo cancellation to and from the host. these signals can be used in concurrent voice and data applications such as host-controlled dsvd by the host. signals supported are serial data output (s8out), serial data in (sr8in), serial shift clock (sr4clk), and sample shift clock (sa4clk). analog voice on the micv input pin is converted to 16-bit linear or 8-bit a-law/-law pcm digital voice samples and output on the sr8out pin to the host. digital voice in 16-bit linear or 8-bit a-law/-law pcm form is received from the host on the sr8in pin, converted to analog form and routed to the spk output pin. sa4clk provides the bit clock used to shift data bits in on the sr8in pin and out on the sr8out pin. sr8clk provides the frame clock used to synchronize words shifted in on the sr8in pin and shifted out on the sr8out pin. audiospan mode (sp models) audiospan provides full-duplex analog simultaneous audio/voice and data over a single telephone line at a data rate with audio of 4800 bps using v.61 modulation. audiospan can send any type of audio waveform, including music. data can be sent with or without error correction. the audio/voice interface can be in the form of a headset, handset, or a microphone and speaker (half- duplex speakerphone). handset echo cancellation is provided. data formats serial synchronous data data rate: 300-56000 bps (rp56), 300-33600 bps (rp56 and rp336), or 300-14400 bps, 0.01%. selectable clock: internal, external, or slave. serial asynchronous data data rate: 300-56000 bps (rp56), 300-33600 bps (rp56 and rp336), or 300-14400 bps, +1% (or +2.3%), -2.5%; 0-300 bps (v.21 and bell 103); 1200/75 bps (v.23). bits per character: 7, 8, 9, 10, or 11. parallel synchronous data normal sync: 8-bit data for transmit and receive data rate: 300-56000 bps (rp56), 300-33600 bps (rp56 and rp336), or 300-14400 bps, 0.01%. sdlc/hdlc support: transmitter: flag generation, 0 bit stuffing, crc-16 or crc-32 generation. receiver: flag detection, 0 bit deletion, crc-16 or crc-32 checking.
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' parallel asynchronous data data rate: 300-56000 bps (rp56), 300-33600 bps (rp56 and rp336), or 300-14400 bps, +1% (or 2.3%), -2.5%; 1200, 300, or 75 bps (fsk). data bits per character: 5, 6, 7, or 8. parity generation/checking: odd, even, or 9th data bit. async/sync and sync/async conversion an asynchronous-to-synchronous converter is provided in the transmitter and a synchronous-to-asynchronous converter is provided in the receiver. the converters operate in both serial and parallel modes. the asynchronous character format is 1 start bit, 5 to 8 data bits, an optional parity bit, and 1 or 2 stop bits. valid character size, including all bits, is 7, 8, 9, 10, or 11 bits per character. two ranges of signaling rates are provided: basic range: +1% to C2.5% extended overspeed range: +2.3% to C2.5% when the transmitter's converter is operating at the basic signaling rate, no more than one stop bit will be deleted per 8 consecutive characters. when operating at the extended rate, no more than one stop bit will be deleted per 4 consecutive characters. break handling is performed as described in v.14. asynchronous characters are accepted on the txd serial input and are issued on the rxd serial output. v.54 inter-dce signaling the mdp supports v.54 inter-dce signaling procedures in synchronous and asynchronous configurations. transmission and detection of the preparatory, acknowledgment, and termination phases as defined in v.54 are provided. three control bits in the transmitter allow the host to send the appropriate bit patterns (v54t, v54a, and v54p bits). three control bits in the receiver are used to enable one of three bit pattern detectors (v54te, v54ae, and v54pe bits). a status bit indicates when the selected pattern detector has found the corresponding bit pattern (v54dt bit). v.13 remote rts signaling the mdp supports v.13 remote rts signaling. transmission and detection of signaling bit patterns in response to a change of state in the rts bit or the ~rts input signal are provided. the rrtse bit enables v.13 signaling. the rtsde bit enables detection of v.13 patterns. the rtsdt status bit indicates the state of the remote rts signal. this feature may be used to clamp/unclamp the local ~rlsd and rxd signals in response to a change in the remote rts signal in order to simulate controlled carrier operation in a constant carrier environment. the mdp automatically clamps and unclamps ~rlsd. dialing and answering the host can dial and answer using supported dtmf/pulse dialing and tone detection functions. the major parameters are host programmable. supervisory tone detection three parallel tone detectors (a, b, and c) are provided for supervisory tone detection. the signal path to these detectors is separate from the main received signal path. each tone detector consists of two cascaded second order iir biquad filters. the coefficients are host programmable. each fourth order filter is followed by a level detector which has host programmable turn-on and turn-off thresholds allowing hysteresis. tone detector c is preceded by a prefilter and squarer. this circuit is useful for detecting a tone with frequency equal to the difference between two tones that may be simultaneously present on the line. the squarer may be disabled by the sqdis bit causing tone detector c to be an eighth order filter. the tone detectors are disabled in data mode. the tone detection sample rate is 9600 hz in v.8 and v.34 modes and is 7200 hz in non-v.34 modes. the default call progress filter coefficients are based on a 7200 hz sampling rate and apply to non-v.34 modes only. the maximum detection bandwidth is equal to one-half the sample rate. the default bandwidths and thresholds of the tone detectors are: tone detector bandwidth turn-on threshold turn-off threshold a 245 C 650 hz C25 dbm C31 dbm b 360 C 440 hz C25 dbm C31 dbm c prefilter 0 C 500 hz n/a n/a c 50 C 110 hz * * * tone detector c will detect a difference tone within its bandwidth when the two tones present are in the range C1 dbm to C26 dbm. 511 pattern generation/detection in synchronous mode, a 511 pattern can be generated and detected (control bit s511). use of this bit pattern during self-test eliminates the need for external test equipment. in-band secondary channel a full-duplex in-band secondary channel is provided in v.34 (all speeds) and v.32 bis/v.32 (7200 bps and above) modes. control bit secen enables and disables the secondary channel operation. the secondary channel operates in parallel data mode with independent transmit and receive interrupts and data buffers. the main channel may operate in parallel or serial mode. in v.34 modes, the secondary channel rate is 200 bps. in v.32 bis/v.32 modes, the secondary channel rate is 150 bps. this rate is also host programmable in v.32 bis/v.32 modes. transmit and receive fifo data buffers two (16+128)-byte first-in first-out (fifo) data buffers allow the dte/host to rapidly output up to 144 bytes of transmit data and input up to 144 bytes of accumulated received data. the receiver fifo is always enabled. the transmitter fifo is enabled by the fifoen control bit. txhf and rxhf bits operate off the lower 16 bits and
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' indicate the corresponding fifo buffer half full (8 or more bytes loaded) status. txfnf and rxfne bits indicate the txfifo buffer not full and rxfifo buffer not empty status, respectively. an interrupt mask register allows an interrupt request to be generated whenever the txfnf, rxfne, rxhf, or txhf status bit changes state. the 128-byte fifo extensions are enabled by default and can be disabled by clearing a bit in ram. dma support interrupt request lines dma support is available in synchronous, asynchronous, and hdlc parallel data modes. control bit dmae enables and disables dma support. when dma support is enabled, the mdp ~ri and ~dsr lines are assigned to transmitter request (txrq) and receiver request (rxrq) hardware output interrupt request lines, respectively. the txrq and rxrq signals follow the assertion of the tdbe and rdbf interrupt bits thus allowing the dte/host to respond immediately to the interrupt request without masking out status bits to determine the interrupt source. nrzi encoding/decoding nrzi data encoding/decoding may be selected in synchronous and hdlc modes instead of the default nrz (control bit nrzien). in nrz encoding, a 1 is represented by a high level and a 0 is represented by a low level. in nrzi encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. itu-t crc-32 support itu-t crc-32 generation/checking may be selected instead of the default itu-t crc-16 in hdlc mode using dsp ram access. caller id demodulation caller id information can be demodulated in v.23 1200 receive configuration and presented to the host/dte in serial (rxd) and parallel (rbuffer) form. telephone line interface line transformer interface. v.90/k56flex/v.34/v.32 bis/v.32 places high requirements upon the data access arrangement (daa) to the telephone line. any non-linear distortion generated by the daa in the transmit direction cannot be canceled by the mdp's echo canceller and interferes with data reception. the designer must, therefore, ensure that the total harmonic distortion seen at the rxa input to the mdp be at least 65 db below the minimum level of received signal. due to the wider bandwidth requirements in v.90, k56flex, and v.34, the daa must maintain linearity from 10 hz to 4000 hz. relay control. direct control of the off-hook and talk/data relays is provided. internal relay drivers allow direct connection to the off-hook (rlya) and talk/data (rlyb) relays. the talk/data relay output can optionally be used for pulse dial. speaker interface an analog speaker output (spk) is provided with on/off and volume control logic incorporated in the mdp. an external amplifier is recommended if driving non-amplified speakers. a digital speaker output (spkmd) is provided which reflects the received analog input signal digitized to ttl high or low level by an internal comparator to create a pc card (pcmcia)-compatible signal. additional information additional information is provided in the RP56LD, rp336ld, and rp144ld modem designer's guide (order no. 1155). hardware interface signals a functional interconnect diagram showing the typical mdp connection in a system is illustrated in figure 2. any point that is active low is represented by a small circle at the signal point. edge triggered inputs are denoted by a small triangle (e.g., tdclk). an active low signal is indicated by a tilde preceding the signal name (e.g., ~reset). a clock intended to activate logic on its rising edge (low- to-high transition) is called active low (e.g., ~rdclk), while a clock intended to activate logic on its falling edge (high-to-low transition) is called active high (e.g., tdclk). when a clock input is associated with a small circle, the input activates on a falling edge. if no circle is shown, the input activates on a rising edge. the 144-pin tqfp mdp hardware interface signals are shown figure 2. the 144-pin tqfp mdp signal pin assignments are shown figure 3 and are listed in table 4. the 100-pin pqfp mdp hardware interface signals are shown figure 4. the 100-pin pqfp mdp signal pin assignments are shown figure 5 and are listed in table 5. the mdp hardware interface signals are described in table 6. the digital interface characteristics are defined in table 7. the analog interface characteristics are defined table 8. the power requirements are defined in table 9. the absolute maximum ratings are defined in table 10.
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' 122 123 7 144 1 3 4 6 8 9 10 11 12 64 65 66 67 68 69 130 72 86 32 4.7h 10% 15pf (56.448 mhz)/ 56pf (28.224 mhz) 5% 10pf (56.448 mhz)/ 18pf (28.224 mhz) 5% * 115 140 141 143 xtli xtlo 48 35 128 30 25 26 20 22 29 33 24 36 34 40 ~rlya ~rlyb ringd rin txa1 txa2 telin/nc* telout/nc* micv/nc* micm spk spkmd micbias ~set3v 56.448 mhz/ 28.224 mhz notes: 1. tolerances and ratings (unless otherwise specified): resistor values in ohms; 5%, 1/8w capacitor values in microfarads; 10%, 20v 2. denotes analog ground. 3. denotes digital ground. telephone line/ telephone/ audio interface agnd agnd agnd agnd agndm agndv/nc* vsub yclk xclk syclk d0 d1 d2 d3 d4 d5 d6 d7 rs0 rs1 rs2 rs3 rs4 ~cs ~write ~read irq ~wkres ~res1 ~res2 mcu: ~wkresout mcu external bus mcu: irq mclkin mtxsin mrxout mstrobe msclk mcntrlsin sr1io ia1clk sa1clk sr4in sr4out clkout sr3out sr3in sa2clk sr2clk sr2io vcntrlsin/nc* vsclk/nc* vstrobe/nc* vrxout/nc* vtxsin/nc* vclkin/nc* 43 44 46 47 45 42 106 94 93 89 87 91 88 90 103 73 104 58 55 53 54 56 57 sleepo iasleep 113 59 nc tiro2 vgg avdd avdd vdd vdd vdd vdd gnd gnd gnd gnd gnd gnd 74 117 37 50 79 107 137 138 52 60 84 109 121 132 +3.3v 0.1 10 10 14 18 19 49 31 21 51 10h +5v or +3.3v (+5v recommended) avaa 23 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 63 80 82 101 102 105 110 114 116 118 119 120 126 131 135 136 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc reserved reserved nc nc nc nc nc nc nc nc 2 5 15 16 17 41 70 81 83 142 nc nc nc nc nc nc nc nc nc nc gpo0 ~rdclk tdclk xtclk txd rxd ~rts ~cts ~dtr ~dsr ~rlsd ~ri sr8out sr8in sr4clk sa4clk 134 71 76 108 77 111 129 78 112 125 75 127 100 99 98 97 serial dte interface 139 96 62 124 95 92 38 39 reserved reserved reserved reserved reserved reserved reserved/nc* reserved/nc* nc nc nc nc nc nc nc nc mk4 mk5 pllvdd pllgnd 133 85 13 61 md212f2 his +5v/+3.3v (highest available) noxtl clkin mcu: ~reset agnd (vaa = +3.3v or nc (vaa = +5v) 10 +3.3v (vdd) 10 0.022 0.1 note differences in vc and pllvdd, circuit gnd/agnd connections for 144-pin tqfp and and 100-pin pqfp. provide direct connection or ferrite bead between gnd and agnd, whichever achieves lowest noise floor. fb 10pf (56.448 mhz)/ 18pf (28.224 mhz) 5% * 10 0.1 cer vref 27 10 0.1 cer vc 28 daa for external vc use host voice serial interface * component values shown in the crystal circuit are typical and may require slightly different values to compensate for stray capacitance and crystal characteristic differences. it is good practice to tune the crystal frequency within +/- 0.002% tolerance at room temperature. the tdclk clock may be measured for accuracy in order not to affect the oscillator with probe capacitance. the default tdclk frequency is 14.4 khz. adjust the load capacitors equally such that tdclk is within 14.4 khz +/- 0.3 hz. * pins are internal no connect (nc) on non-sp models. )ljxuh 0'3 +dugzduh ,qwhuidfh 6ljqdov3lq 74)3
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' md212f3 po-r6785-144t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 d1 reserved d2 d3 reserved d4 syclk d5 d6 d7 rs0 rs1 pllvdd agnd nc nc nc agnd agnd telin/nc* agndv/nc* telout/nc* avaa spk txa1 txa2 vref vc micv/nc* rin agndm ~res2 micm m icbias ~rlyb spkm d xtclk vdd sr1io reserved sr2io sa2clk reserved reserved sr8out sr8in sr4clk sa4clk reserved reserved ia1clk sa1clk reserved clkout sr3in sr4in sr3out sr4out ~res1 m k5 gnd nc reserved nc reserved vdd ~cts txd tdclk ~rlsd tiro2 sr2clk d0 xtlo nc xtli clkin reserved vdd vdd reserved reserved gp00 mk4 gnd reserved irq ~rts ringd ~ri reserved ~dsr reserved xclk yclk gnd reserved reserved reserved vgg reserved noxtl reserved sleepo ~dtr rxd reserved gnd avdd ~vrlya/nc* ~vrlyb/nc* ~set3v nc m cntrlsin mclkin mtxsin msclk m rxout m strobe ~rlya agnd avdd vsub gnd vstrobe/nc* vrxout/nc* vsclk/nc* vtxsin/nc* vclkin/nc* vcntrlsin/nc* iasleep gnd pllgnd reserved reserved rs2 rs3 rs4 ~cs ~w rite ~read nc ~rdclk ~w kres * nc on non-sp models. )ljxuh 0'3 3lq 6ljqdov 3lq 74)3
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' 7deoh 0'3 3lq 6ljqdov 3lq 74)3 pin signal label i/o type interface 3 pin signal label i/o type interface 1 d1 ia/ob host parallel interface 73 sr2clk di to vsclk (55) 2 reserved nc 74 tiro2 ia nc 3 d2 ia/ob host parallel interface 75 ~rlsd oa dte serial interface 4 d3 ia/ob host parallel interface 76 tdclk oa dte serial interface 5 reserved nc 77 txd ia dte serial interface 6 d4 ia/ob host parallel interface 78 ~cts oa dte serial interface 7 syclk oa controller 79 vdd pwr +3.3v 8 d5 ia/ob host parallel interface 80 reserved nc 9 d6 ia/ob host parallel interface 81 nc nc 10 d7 ia/ob host parallel interface 82 reserved nc 11 rs0 ia host parallel interface 83 nc nc 12 rs1 ia host parallel interface 84 gnd gnd dgnd 13 pllvdd pll to +3.3 (vdd) through 10 w and to agnd though10 m f 85 mk5 ia pll circuit select (note 4) 14 agnd gnd agnd 86 ~res1 pif: ~reset sif: reset circuit 15 nc nc 87 sr4out di to mtxsin (44) 16 nc nc 88 sr3out di to vtxsin (56) 17 nc nc 89 sr4in di to mrxout (46) 18 agnd gnd agnd 90 sr3in di to vrxout (54) 19 agnd gnd agnd 91 clkout di to mclkin (43) & vclkin (57) 20 telin/nc* i(da) line/audio interface 92 reserved nc 21 agndv/nc* gnd agnd 93 sa1clk di to mstrobe (47) 22 telout/nc* o(dd) line/audio interface 94 ia1clk di to msclk (45) 23 avaa pwr +3.3va or +5va 95 reserved nc 24 spk o(df) line/audio interface 96 reserved nc 25 txa1 o(dd) line/audio interface 97 sa4clk oa host voice serial interface 26 txa2 o(dd) line/audio interface 98 sr4clk oa host voice serial interface 27 vref ref vc through capacitors 99 sr8in ia host voice serial interface 28 vc ref daa; agnd thru capacitors 100 sr8out oa host voice serial interface 29 micv/nc* i(da) line/audio interface 101 reserved nc 30 rin i(da) line/audio interface 102 reserved nc 31 agndm gnd agnd 103 sa2clk di to vstrobe (53) 32 ~res2 pif: ~reset sif: reset circuit 104 sr2io di to vcntrlsin (58) 33 micm i(da) line/audio interface 105 reserved nc 34 micbias micbias circuit 106 sr1io di to mcntrlsin (42) 35 ~rlyb od line/audio interface 107 vdd pwr +3.3v 36 spkmd oa line/audio interface 108 xtclk ia dte serial interface 37 avdd pwr +3.3v 109 gnd gnd dgnd 38 reserved/nc* nc 110 reserved nc 39 reserved/nc* nc 111 rxd oa dte serial interface 40 ~set3v ia agnd (vaa = +3.3v) or nc (vaa = +5v) 112 ~dtr ia dte serial interface 41 nc nc 113 sleepo di to iasleep (59) 42 mcntrlsin di to sr1io (106) 114 reserved nc 43 mclkin di to clkout (91) 115 noxtl ia vcc or gnd 44 mtxsin di to sr4out (87) 116 reserved nc 45 msclk di to ia1clk (94) 117 vgg ref +5v or +3.3v 46 mrxout di to sr4in (89) 118 reserved nc 47 mstrobe di to sa1clk (93) 119 reserved nc 48 ~rlya od line/audio interface 120 reserved nc 49 agnd gnd agnd 121 gnd gnd dgnd 50 avdd pwr +3.3v 122 yclk oa nc 51 vsub gnd agnd 123 xclk oa nc 52 gnd gnd dgnd 124 reserved nc 53 vstrobe/nc* di to sa2clk (103) 125 ~dsr oa dte serial interface 54 vrxout/nc* di to sr3in (90) 126 reserved nc 55 vsclk/nc* di to sr2clk (73) 127 ~ri oa dte serial interface 56 vtxsin/nc* di to sr3out (88) 128 ringd ia line/audio interface 57 vclkin/nc* di to clkout (91) 129 ~rts ia dte serial interface 58 vcntrlsin/nc* di to sr2io (104) 130 irq ia host parallel interface 59 iasleep di to sleepo (113) 131 reserved nc 60 gnd gnd dgnd 132 gnd gnd dgnd
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' 7deoh 0'3 3lq 6ljqdov 3lq 74)3 &rqwg pin signal label i/o type interface3 pin signal label i/o type interface 61 pllgnd pll agnd 133 mk4 ia pll circuit select (note 4) 62 reserved nc 134 gp00 di to ~rdclk (71) 63 reserved nc 135 reserved nc 64 rs2 ia host parallel interface 136 reserved nc 65 rs3 ia host parallel interface 137 vdd pwr +3.3v 66 rs4 ia host parallel interface 138 vdd pwr +3.3v 67 ~cs ia host parallel interface 139 reserved nc 68 ~write ia host parallel interface 140 clkin ia clock circuit 69 ~read ia host parallel interface 141 xtli i crystal circuit 70 nc nc 142 nc nc 71 ~rdclk oa dte serial interface 143 xtlo o crystal circuit 72 ~wkres ia mcu: ready/~wkresout 144 d0 ia/ob host parallel interface notes: 1. i/o types: ia, ib = digital input; oa, ob = digital output. i(da) = analog input; o(dd), o(df) = analog output. di = device interconnect. 2. nc = no internal pin connection; reserved = no external connection allowed (may have internal connection). 3. interface legend: mdp = modem data pump dte = data terminal equipment pif = parallel host interface sif = serial dte interface. 4. an internal 55 k w pullup resistor is connected to this pin. * nc on non-sp models.
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' 75 76 88 89 90 91 92 93 94 95 96 97 2 3 4 5 6 7 80 9 36 17 47 79 35 30 31 26 27 34 37 29 38 ~rlya ringd rin txa1 txa2 telin/nc* telout/nc* micv/nc* micm spk spkmd notes: 1. tolerances and ratings (unless otherwise specified): resistor values in ohms; 5%, 1/8w capacitor values in microfarads; 10%, 20v 2. denotes analog ground. 3. denotes digital ground. telephone line/ telephone/ audio interface agnd agnd agnd yclk xclk d0 d1 d2 d3 d4 d5 d6 d7 rs0 rs1 rs2 rs3 rs4 ~cs ~write ~read irq ~wkres ~res2 ~res1 mcu: ~wkresout mcu external bus mcu: irq mclkin mtxsin mrxout mstrobe msclk mcntrlsin sr1io ia1clk sa1clk sr4in sr4out clkout sr3out sr3in sa2clk sr2clk sr2io vcntrlsin/nc* vsclk/nc* vstrobe/nc* vrxout/nc* vtxsin/nc* vclkin/nc* 42 43 45 46 44 41 62 24 23 20 18 22 19 21 59 10 60 55 52 50 51 53 54 sleepo iasleep 69 56 10 0.1 cer vref 32 10 0.1 cer vc 33 14 15 1 57 61 66 70 72 73 74 77 83 84 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved avdd vdd vdd vdd gnd gnd gnd gnd gnd 40 63 68 85 16 65 81 99 49 +3.3v 0.1 10 0.022 10 25 39 48 10h avaa 28 gpo0 ~rdclk tdclk xtclk txd rxd ~rlsd ~ri 82 8 12 64 13 67 11 78 serial dte interface nc nc nc nc nc nc nc nc nc nc nc nc nc pllvdd pllgnd 98 100 md212f4-his-100pqfp +5v/+3.3v (highest available) 58 71 reserved vgg mcu: ~reset 86 87 clkin nc 28.224 mhz clock nc * pins are internal no connect (nc) on non-sp models. nc +5v or +3.3v (+5v recommended) provide direct connection or ferrite bead between gnd and agnd, whichever achieves lowest noise floor. 0.1 10 +3.3v (vdd) 10 note differences in vc and pllvdd, circuit gnd/agnd connections for 144-pin tqfp and and 100-pin pqfp. daa for external vc use 10h 10h 10h ferrite beads (70 ohm @ 100 mhz type with a max dc resistance of 0.5 ohm and a rated current of 200 ma). fb fb fb *** component values shown in the crystal circuit are typical and may require slightly different values to compensate for stray capacitance and crystal characteristic differences. it is good practice to tune the crystal frequency within +/- 0.002% tolerance at room temperature. the tdclk clock may be measured for accuracy in order not to affect the oscillator with probe capacitance. the default tdclk frequency is 14.4 khz. adjust the load capacitors equally such that tdclk is within 14.4 khz +/- 0.3 hz. )ljxuh 0'3 +dugzduh ,qwhuidfh 6ljqdov3lq 34)3
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' md212f5 po-r6764-100p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 pllgnd gnd pllvdd rs1 rs0 d7 d6 d5 d4 d3 d2 d1 d0 nc clkin vdd reserved reserved gp00 gnd txa2 vref vc micv/nc* rin ~res2 micm spkmd agnd avdd mcntrlsin mclkin mtxsin msclk mrxout mstrobe ~rlya agnd gnd vstrobe/nc* irq ringd ~ri reserved xclk yclk reserved reserved reserved vgg reserved sleepo vdd rxd reserved gnd xtclk vdd sr1io reserved sr2io sa2clk reserved reserved iasleep vcntrlsin/nc* vclkin/nc* vtxsin/nc* vsclk/nc* vrxout/nc* reserved rs2 rs3 rs4 ~cs ~write ~read ~rdclk ~wkres sr2clk ~rlsd tdclk txd reserved reserved gnd ~res1 sr4out sr3out sr4in sr3in clkout sa1clk ia1clk agnd telin/nc* telout/nc* avaa spkr txa1 * nc on non-sp models. )ljxuh 0'3 3lq 6ljqdov 3lq 34)3
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' 7deoh 0'3 3lq 6ljqdov 3lq 34)3 pin signal label i/o type interface 3 pin signal label i/o type interface 1 reserved nc 51 vrxout/nc* di to sr3in (21) 2 rs2 ia host parallel interface 52 vsclk/nc* di to sr2clk (10) 3 rs3 ia host parallel interface 53 vtxsin/nc* di to sr3out (19) 4 rs4 ia host parallel interface 54 vclkin/nc* di to clkout (22) 5 ~cs ia host parallel interface 55 vcntrlsin/nc* di to sr2io (60) 6 ~write ia host parallel interface 56 iasleep di to sleepo (69) 7 ~read ia host parallel interface 57 reserved nc 8 ~rdclk oa dte serial interface 58 reserved nc 9 ~wkres ia mcu: ready/~wkresout 59 sa2clk di to vstrobe (50) 10 sr2clk di to vsclk (52) 60 sr2io di to vcntrlsin (55) 11 ~rlsd oa dte serial interface 61 reserved nc 12 tdclk oa dte serial interface 62 sr1io di to mcntrlsin (41) 13 txd ia dte serial interface 63 vdd pwr +3.3v 14 reserved nc 64 xtclk ia dte serial interface 15 reserved nc 65 gnd gnd dgnd 16 gnd gnd dgnd 66 reserved nc 17 ~res1 pif: ~reset sif: reset circuit 67 rxd oa dte serial interface 18 sr4out di to mtxsin (43) 68 vdd pwr +3.3v 19 sr3out di to vtxsin (53) 69 sleepo di to iasleep (56) 20 sr4in di to mrxout (45) 70 reserved nc 21 sr3in di to vrxout (51) 71 vgg ref +5v or +3.3v 22 clkout di to mclkin (42) & vclkin (54) 72 reserved nc 23 sa1clk di to mstrobe (46) 73 reserved nc 24 ia1clk di to msclk (44) 74 reserved nc 25 agnd gnd analog ground 75 yclk oa nc 26 telin/nc* i(da) line/audio interface 76 xclk oa nc 27 telout/nc* o(dd) line/audio interface 77 reserved nc 28 avaa pwr +3.3va or +5va 78 ~ri oa dte serial interface 29 spk o(df) line/audio interface 79 ringd ia line/audio interface 30 txa1 o(dd) line/audio interface 80 irq ia host parallel interface 31 txa2 o(dd) line/audio interface 81 gnd gnd dgnd 32 vref ref vc through capacitors 82 gp00 di to ~rdclk (8) 33 vc ref daa through fb; gnd through capacitors and fb 83 reserved nc 34 micv/nc* i(da) line/audio interface 84 reserved nc 35 rin i(da) line/audio interface 85 vdd pwr +3.3v 36 ~res2 pif: ~reset sif: reset circuit 86 clkin i clock circuit 37 micm i(da) line/audio interface 87 nc nc 38 spkmd oa line/audio interface 88 d0 ia/ob host parallel interface 39 agnd gnd analog ground 89 d1 ia/ob host parallel interface 40 avdd pwr +3.3v 90 d2 ia/ob host parallel interface 41 mcntrlsin di to sr1io (62) 91 d3 ia/ob host parallel interface 42 mclkin di to clkout (22) 92 d4 ia/ob host parallel interface 43 mtxsin di to sr4out (18) 93 d5 ia/ob host parallel interface 44 msclk di to ia1clk (24) 94 d6 ia/ob host parallel interface 45 mrxout di to sr4in (20) 95 d7 ia/ob host parallel interface 46 mstrobe di to sa1clk (23) 96 rs0 ia host parallel interface 47 ~rlya od nc 97 rs1 ia host parallel interface 48 agnd gnd agnd 98 pllvdd pll to +3.3 (vdd) through 10 w and to dgnd through 10 m f. 49 gnd gnd dgnd 99 gnd gnd dgnd 50 vstrobe/nc* di to sa2clk (59) 100 pllgnd pll dgnd notes: 1. i/o types: ia, ib = digital input; oa, ob = digital output. i(da) = analog input; o(dd), o(df) = analog output. di = device interconnect. 2. nc = no internal pin connection; reserved = no external connection allowed (may have internal connection). 3. interface legend: mdp = modem data pump dte = data terminal equipment pif = parallel host interface sif = serial dte interface. * nc on non-sp models.
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' 7deoh 0'3 6ljqdo 'hilqlwlrqv label i/o type signal/definition overhead signals clkin ia clock in (144-pin tqfp). if external clock is selected (noxtl = low), connect to an external 56.448 mhz or 28.224 mhz clock circuit. the clock frequency is selected by the mk4 and mk5 inputs. xtli i crystal in (144-pin tqfp). if external crystal is selected (noxtl = high), connect to an external 56.448 mhz or 28.224 mhz crystal circuit. the clock frequency is selected by the mk4 and mk5 inputs. xtlo o crystal out (144-pin tqfp). if external crystal is selected (noxtl = high), connect to the external crystal circuit return. noxtl ia no crystal circuit (144-pin tqfp). selects external crystal (noxtl = high, i.e., leave open or connect to vdd through 10k w ) or clock (noxtl = low, i.e., connect to gnd) circuit. internal pull-up provided. xtli/clkin i crystal in/clock in (100-pin pqfp). connect to an external 56.448 mhz/28.224 mhz crystal circuit (crystal input option) or to an external 56.448 mhz/28.224 mhz clock circuit (clock input option). xtlo/nc o crystal out/nc (100-pin pqfp). connect to the external crystal circuit return (crystal input option) or leave open (clock input option). ~res1, ~res2 ia reset. ~reset low holds the mdp in the reset state. ~reset going high releases the mdp from the reset state and initiates normal operation using power turn-on (default) values. ~reset must be held low for at least 3 s. the mdp is ready to use 400 ms after the low-to-high transition of ~reset. ~res1 and ~res2 are typically connected to the mcu ~reset input and to the host bus ~reset (or reset through an inverter) line (parallel host) or reset circuit (serial dte interface) which resets both the mcu and mdp upon power turn-on. ~res1 and ~res2 have active internal pull-up resistors. ~wkres ia wake-up reset. ~wkres is connected internally to ~reset but will not drive the mdp ~reset pins. asserting ~wkres performs the same reset function as the mdp ~reset and typically used by the mcu to wake up the mdp from sleep mode when the mdp ~reset lines cannot be asserted (because they are also connected to the mcu ~reset input). for a serial dte or parallel host mcu configuration, connect ~wkres to the mcu ~wkresout output. ~wkres has an active internal pull-up resistor. vdd pwr +3.3v digital circuit power supply. connect to +3.3v through digital circuit power supply filter. avdd pwr +3.3v analog circuit digital power supply. connect to +3.3v through digital circuit power supply filter. avaa pwr analog circuit analog power supply. connect to +3.3v or +5v (preferred) through analog circuit power supply filter. note: when operating the analog circuitry at +3.3v, the transmit level is 4 db lower and the converted receive level is 4 db higher when compared to operating the analog circuitry at +5v. the transmit level must be adjusted accordingly using tlvl or other means. vgg ref input reference voltage. reference voltage for +5v tolerant input pins. connect to the highest of +3.3v or +5v available on the circuit board. a connection to +5v allows +5v or +3.3v input levels. a connection to +3.3v allows +3.3v input levels only. gnd gnd digital ground. connect to digital ground. agnd gnd analog ground. connect to analog ground. xclk oa x clock. output clock at 56.448 mhz (pll disabled) or 63.5045 (pll enabled), which runs during mdp normal mode and is turned off during sleep mode. yclk oa y clock. output clock at 28.224 mhz, which runs during mdp normal mode and is turned off during sleep mode. syclk oa system clock. output clock at 28.224 mhz, which runs during mdp normal mode and during sleep mode. pllvdd pll pllvdd connection. for the 144-pin tqfp, connect to +3.3v (vdd) through 10 w and to agnd through 10 (+) m f, for the 100-pin pqfp, connect to +3.3v (vdd) through 10 w and to dgnd through 10 (+) m f. pllgnd pll pllgnd connection. for the 144-pin tqfp, connect to agnd. for the 100-pin pqfp, connect to dgnd. ~set3v ia set integrated analog +3.3v reference. selects analog circuit voltage reference: high (nc) = +5v, low (agnd) = +3.3v.
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' 7deoh 0'3 6ljqdo 'hilqlwlrqv &rqw
g label i/o type signal name/description overhead signals (continued) mk4 ia pll circuit enable/disable (144-pin tqfp). this pin disables (mk4 = high) or enables (mk4 = low, recommended setting) the internal pll circuit. connect this pin to gnd to enable the pll circuit. internal pull-up provided. mk4 must be low if using the 28.224 mhz option. see mk5. note: the 100-pin pqfp is internally bonded to enable the internal pll. mk5 ia pll circuit frequency select (144-pin tqfp). this pin selects the input frequency (mk5 high = 28.224 mhz, mk5 low = 56.448 mhz) when the internal pll circuit is enabled (mk4 = low). if the pll is disabled (mk4 = high), leave mk5 high and use 56.448 mhz. internal pull-up provided. see mk4. if 28.224 mhz input frequency is used, mk4 must be low and mk5 must be high. note: the 100-pin pqfp is internally bonded to select a 28.224 mhz input frequency. mk4 mk5 pll enabled crystal/clock 0 0 yes 56.448 mhz 0 1 yes 28.224 mhz (most common) 1 0 no invalid option 1 1 no 56.448 mhz parallel host interface address, data, control, and interrupt hardware interface signals allow mdp connection to an 8086-compatible microprocessor bus. with the addition of external logic, the interface can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or 68000. the microprocessor interface allows a microprocessor to change mdp configuration, read or write channel and diagnostic d ata, and supervise mdp operation by writing control bits and reading status bits. d0Cd7 ia/ob data lines. eight bidirectional data lines (d0Cd7) provide parallel transfer of data between the host and the mdp. the most significant bit is d7. data direction is controlled by the read enable and write enable signals. rs0Crs4 ia register select lines. the five active high register select lines (rs0Crs4) address internal mdp interface memory registers and are typically connected to the five least significant lines (a0Ca4) of the address bus. the mdp decodes rs0 through rs4 to address one of 32 internal interface memory registers (00C1f). the most significant address bit is rs4, while the least significant address bit is rs0. the selected register can be read from or written into via the 8-bit parallel data bus (d0Cd7). the most significant data bit is d7, while the least significant data bit is d0. ~cs ia chip select. ~cs selects the mdp for microprocessor bus operation. ~cs is typically generated by decoding host address bus lines. ~read ia read enable. during a read cycle (~read asserted), data from the selected interface memory register is gated onto the data bus by means of three-state drivers in the mdp. these drivers force the data lines high for a one bit, or low for a zero bit. when not being read, the three-state drivers assume their high-impedance (off) state. ~write ia write enable. during a write cycle (~write asserted), data from the data bus is copied into the selected mdp interface memory register, with high and low bus levels representing one and zero bit states, respectively. irq oa i nterrupt request. the mdp irq output may be connected to the host processor interrupt request input in order to interrupt host program execution for immediate mdp service. the irq output can be enabled in the mdp interface memory to indicate immediate change of conditions. the use of irq is optional depending upon mdp application. the irq output is driven by a ttl-compatible cmos driver. voice serial interface (144-pin r6785; sp model) timing and data signals provide a voice serial interface which is used to transfer 16-bit linear or 8-bit a-law/-law pcm voice samples in full- duplex speakerphone form with acoustic echo cancellation to and from the host. these signals can be used in concurrent voice an d data applications by the host. in non-sp models, voice samples are not supported on these pins and these pins should be left open. sr8out oa serial data out. analog voice on the micv input pin is converted to 16-bit linear or 8-bit a-law/-law pcm digital voice samples and output on this pin in serial form to the host. sr8in in serial data in. digital voice in 16-bit linear or 8-bit a-law/-law pcm form is received from the host on this serial data input pin, converted to analog form and routed to the spkr output pin. sr4clk ia serial shift clock. serial bit clock used to shift data bits into the mdp on the sr8in pin and out of the mdp on the sr8out pin. connect to mdp clkout (pb0) pin. sa4clk ia sample shift clock. serial frame clock used to synchronize words shifted in on the sr8in pin and shifted out on the sr8out pin. sa4clk clock edges must align with the rising edge of sr4clk.
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g label i/o type signal name/description dte serial interface timing, data, control, and status signals provide a v.24-compatible serial interface. these signals are ttl compatible in order to drive the short wire lengths and circuits normally found within a printed circuit board, stand-alone modem enclosures, or equipment cabin ets. for driving longer cables, these signals can be easily converted to eia/rs-232-d voltage levels. txd ia transmitted data. the mdp obtains serial data to be transmitted from the local dte on the transmitted data (txd) input. rxd oa received data. the mdp presents received serial data to the local dte on the received data (rxd) output. ~rts ia request to send. activating ~rts causes the mdp to transmit data on txd when ~cts becomes active. the ~rts pin is logically ored with the rts bit. ~cts oa clear to send. ~cts active indicates to the local dte that the mdp will transmit any data present on txd. cts response times from an active condition of rts are shown in table 3. ~rlsd oa received line signal detector. ~rlsd active indicates to the local dte that energy above the receive level threshold is present on the receiver input, and that the energy is not a training sequence. one of four ~rlsd receive level threshold options can be selected (rth bits). a minimum hysteresis action of 2 db exists between the actual off-to-on and on-to-off transition levels. the threshold level and hysteresis action are measured with a modulated signal applied to the receiver analog (rxa) input. note that performance may be degraded when the received signal level is less than -43 dbm. the ~rlsd on and off thresholds are host programmable in dsp ram. ~dtr ia data terminal ready. in v.8, v.90, k56flex, v.34, v.32 bis, v.32, v.22 bis, v.22, or bell 212a configuration, activating ~dtr initiates the handshake sequence. the data bit must be set to complete the handshake. in v.21, v.23, or bell 103 configuration, activating ~dtr causes the mdp to enter the data state provided that the data bit is a 1. if in answer mode, the mdp immediately sends answer tone. in these modes, if controlled carrier is enabled, carrier is controlled by rts. during the data mode, deactivating ~dtr causes the transmitter and receiver to turn off and return to the idle state. the ~dtr input and the dtr control bit are logically ored. ~dsr oa data set ready. ~dsr on indicates that the mdp is in the data transfer state. ~dsr off indicates that the dte is to disregard all signals appearing on the interchange circuits except ring indicator (~ri). ~dsr is off when the mdp is in a test mode (i.e., local analog or remote digital loopback). the dsr status bit reflects the state of the ~dsr output. ~ri oa ring indicator. ~ri output follows the ringing signal present on the line with a low level (0 v) during the on time, and a high level during the off time coincident with the ringing signal. the ri status bit reflects the state of the ~ri output. tdclk oa transmit data clock. the mdp outputs a synchronous transmit data clock (tdclk) for usrt timing. the tdclk frequency is the data rate (0.01%) with a duty cycle of 501%. the tdclk source can be internal, external (input on xtclk), or slave (to ~rdclk) as selected by txclk bits in interface memory. xtclk ia external transmit clock. in synchronous communication, an external transmit data clock can be connected to the mdp xtclk input. the clock supplied at xtclk must exhibit the same characteristics as tdclk. the xtclk input is then reflected at the tdclk output. ~rdclk oa receive data clock. the mdp outputs a synchronous receive data clock (~rdclk) for usrt timing. the ~rdclk frequency is the data rate (0.01%) with a duty cycle of 501%. the ~ rdclk low-to-high transitions coincide with the center of the received data bits.
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g label i/o type signal name/description telephone line/telephone/audio interface signals and reference voltage txa1, txa2 o(df) transmit analog 1 and 2 output. the txa1 and txa2 outputs are differential outputs 180 degrees out of phase with each other. each output can drive a 300 w load. typically, txa1 and txa2 are connected to the telephone line interface or an optional external hybrid circuit. rin i(da) receive analog input. rin is a single-ended input with 70k w input impedance. typically, rin is connected to telephone line interface or an optional external hybrid circuit. note: if not used, do not tie directly to ground; this input has a bias voltage of +1.35v (vaa = +3.3v) or +2.5v (vaa = +5v). ringd ia ring detect. the ringd input is monitored for pulses in the range of 15 hz to 68 hz. the frequency detection range may be changed by the host in dsp ram. the circuit driving ringd should be a 4n35 optoisolator or equivalent. the circuit driving ringd should not respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 vrms (15 hz to 68 hz) across tip and ring. detected ring signals are reflected on the ~ri output signal as well as the ri bit. ~rlya (~ohrc, ~callid) od relay a control. the ~rlya open drain output can directly drive a reed relay coil with a minimum resistance of 360 ohms (9.2 ma max. @ +3.3v). a clamp diode, such as a 1n4148, should be installed across the relay coil. an external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~rlya is controlled by host setting/resetting of the ra bit. in a typical application, ~rlya is connected to the normally open off-hook relay (~ohrc). in this case, ~rlya active closes the relay to connect the mdp to the telephone line. alternatively, in a typical application, ~rlya is connected to the normally open caller id relay (~callid). when the mdp detects a calling number delivery (cnd) message, the ~rlya output is asserted to close the caller id relay in order to ac couple the cnd information to the mdp rin input (without closing the off-hook relay and allowing loop current flow which would indicate an off-hook condition). ~rlyb (~talk) od relay b control. the ~rlyb open drain output can directly drive a reed relay coil with a minimum resistance of 360 ohms (9.2 ma max. @ 3.3v). a clamp diode, such as a 1n4148, should be installed across the relay coil. an external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~rlyb is controlled by host setting/resetting of the rb bit. in a typical application, ~rlyb is connected to the normally closed talk/data relay (~talk). in this case, ~rlyb active opens the relay to disconnect the handset from the telephone line. micm i(da) modem microphone input. micm is a single-ended microphone input. the input impedance is > 70k w . note: if not used, do not tie directly to ground; this input has a bias voltage of +1.35v (vaa = +3.3v) or +2.5v (vaa = +5v). spk o(df) speaker analog output. the spk analog output can originate from one of five different sources: rin, telin, micm or micv or from the mdps internal voice playback mode. the spk on/off and three levels of attenuation are controlled by bits in dsp ram. when the speaker is turned off, the spk output is clamped to the voltage at the vc pin. the spk output can drive an impedance as low as 300 ohms. in a typical application, the spk output is an input to an external lm386 audio power amplifier. spkmd oa modem speaker digital output. the spkmd digital output reflects the received analog input signal digitized to ttl high or low level by an internal comparator to create a pc card (pcmcia)-compatible signal. vref ref high voltage reference. connect to vc through 10 f (polarized, + terminal to vref) and 0.1 f (ceramic) in parallel. vc ref low voltage reference. for the 144-pin tqfp, connect to agnd through 10 f (polarized, + terminal to vc) and 0.1 f (ceramic) in parallel. for the 100-pin pqfp, connect to a ferrite bead and connect the other end of the ferrite bead to dgnd through 10 f (polarized, + terminal to vc) and 0.1 f (ceramic) in parallel. micv/nc* i(da) voice microphone input. micv is a single-ended microphone input. typically, micv is connected to a microphone output for recording voice e.g., in a speakerphone application. note: if not used, do not tie directly to ground; this input has a bias voltage of +1.35v (vaa = +3.3v) or +2.5v (vaa = +5v). telin/nc* i(da) telephone analog input. telin is a single-ended input with 70k w input impedance. typically, telin is connected to a telephone handset microphone circuit. note: if not used, do not tie directly to ground; this input has a bias voltage of +1.35v (vaa = +3.3v) or +2.5v (vaa = +5v). telout/nc* o(df) telephone analog output. telout is a single-ended output that can drive a 300 w load. typically, telout is connected to a telephone handset speaker circuit. micbias ref microphone bias. microphone bias reference voltage.
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g label i/o type signal name/description miscellaneous tiro2 ia nc reserved reserved function. may be connected to internal circuit. leave open. mdp interconnect gp00 di to ~rdclk. sleepo di to iasleep. iasleep di to sleepo. msclk di to ia1clk. clkout di to mclkin & vclkin. sr1io di to mcntrlsin. sr3in di to vrxout. ia1clk di to msclk. sa1clk di to mstrobe. sr4out di to mtxsin. mclkin di to clkout. vclkin/nc* di to clkout. mstrobe di to sa1clk. vstrobe/nc* di to sa2clk. mcntrlsin di to sr1io. vsclk/nc* di to sr2clk. vcntrlsin/nc* di to sr2io. mrxout di to sr4in. vtxsin/nc* di to sr3out. vrxout/nc* di to sr3in. mtxsin di to sr4out. sr2io di to vcntrlsin. sr4in di to mrxout. sr2clk di to vsclk. sa2clk di to vstrobe. sr3out di to vtxsin. * nc on non-sp models. external interconnects as described can made for the nc pins on non-sp models in case sp models are ever substituted in the application design and sp support is required.
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' 7deoh 'ljlwdo (ohfwulfdo &kdudfwhulvwlfv parameter symbol min. typ. max. units test conditions 1 input high voltage v ih vdc type ia 2.0 C v cc input high current i ih C C 40 a input low voltage v il 0.3 0.8 vdc input low current i il C C 40 a input leakage current i in C C 100 adc v in = 0 to +3.3v, v cc = 3.6v output high voltage v oh CCvdc type oa 2.4 C v cc i load = C 100 a type od i load = 0 ma output low voltage v ol vdc type oa C C 0.4 i load = 1.6 ma type od C C 0.75 i load = 15 ma three-state (off) current i tsi 10 adc v in = 0.4 to v cc -1 7deoh $qdorj (ohfwulfdo &kdudfwhulvwlfv signal name type characteristic value rin, telin, i (da) input impedance > 70k w micm, micv ac input voltage range 1.1 vp-p reference voltage +1.35 vdc (vaa = +3.3v) or +2.5 vdc (vaa = +5v) txa1, txa2, o (dd) minimum load 300 w telout maximum capacitive load 0 f output impedance 10 w ac output voltage range 1.4 vp-p (vaa = +3.3v) or 2.2 vp-p (vaa = +5v) (with reference to ground and a 600 w load) reference voltage +1.35 vdc (vaa = +3.3v) or +2.5 vdc (vaa = +5v) dc offset voltage 200 mv spk o (df) minimum load 300 w maximum capacitive load 0.01 f output impedance 10 w ac output voltage range 1.4 vp-p (vaa = +3.3v) or 2.2 vp-p (vaa = +5v) reference voltage +1.35 vdc (vaa = +3.3v) or +2.5 vdc (vaa = +5v) dc offset voltage 20 mv
53/'53/'dqg53/' /rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 0' 7deoh &xuuhqw dqg 3rzhu 5htxluhphqwv mode typical current (ma) maximum current (ma) typical power (mw) maximum power (mw) notes normal mode 75 84 250 300 f = 28.224 mhz sleep mode 10 33 f = 28.224 mhz stop mode <0.3 <1 f = 0 mhz notes: 1. operating voltage: vdd = +3.3v 0.3v. 2. test conditions: vdd = +3.3v for typical values; vdd = +3.6v for maximum values. 3. input ripple 0.1 vpeak-peak. 4. f = internal frequency. 5. stop mode is the same as sleep mode with clo cks turned off. 7deoh $evroxwh 0d[lpxp 5dwlqjv parameter symbol limits units supply voltage v dd -0.5 to +4.0 v input voltage v in v except xtli -0.5 to (vgg +0.5)* xtli -0.5 to 3.9v operating temperature range t a -0 to +70 c storage temperature range t stg -55 to +125 c analog inputs v in -0.3 to (vaa + 0.5) v voltage applied to outputs in high impedance (off) state v hz -0.5 to (vgg +0.5)* v dc input clamp current i ik 20 ma dc output clamp current i ok 20 ma static discharge voltage (25c) v esd 2500 v latch-up current (25c) i trig 400 ma * vgg = +5.0v 5% or +3.3v 0.3v.
/rz9rowdjh9.ioh[99elv/rz3rzhu0rghp'dwd3xpsv 53/'53/'dqg53/' 0' notes
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